The present invention relates to an integrated circuit device having a passive device, and more particularly to an integrated circuit (IC) having a passive device integrally formed therein.
Generally a nonvolatile memory device comprises a memory cell transistor having a stacked gate, a source and a drain, and a peripheral circuit transistor having a single-layer gate, a source and a drain for driving the memory cell transistor in a peripheral circuit region. The stacked gate of the memory cell transistor comprise a floating gate storing a data, a control gate controlling the floating gate, and an interdielectric layer formed therebetween. The single-layer gate is formed of a single-level conductive layer. But in recent years, the peripheral circuit transistor in a peripheral circuit region also has a stacked gate structure as well as the memory cell transistor. Such is disclosed by Y. Takeuchi, et al in Symposium on VLSI technology Digest of Technical Papers, 1998, pp. 102, 103, entitled: xe2x80x9cA Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1 Gbit Flash Memories.xe2x80x9d
In accordance with this prior art teaching, a first portion of the peripheral circuit transistor gate and a floating gate of the memory cell transistor are formed of a first conductive layer and a second portion of the peripheral circuit transistor gate and the control gate of the memory cell transistor are formed of a second conductive layer. The first portion and the second portion of the peripheral circuit transistor gate are connected with each other through a butting contact. The nonvolatile memory device uses a passive device, e.g., a fuse for repairing a defective memory cell. The fuse is formed of only the second conductive layer, without affecting the first conductive layer thereunder, to prevent the second conductive layer from shorting with the first conductive layer after the fuse is cut, e.g. laser-blown, (opened).
Passive devices including resistors, inductors and capacitors have been integrated recently into semiconductor-based ICs, such as are described by Arbuckle, et al. in Processing technology for integrated passive devices, Solid State Technology, November 2000, familiarity with which is assumed.
A layout (plan) view in FIG. 1 and cross-sectional views in FIGS. 2-5 illustrate the nonvolatile memory device including a fuse formed of a second conductive layer, and a method relating thereto.
FIG. 1 is a layout view illustrating the passive device region 10 including a fuse 11, a peripheral circuit transistor (peri-transistor) region 12 having a peripheral transistor 18, and a memory cell array region 14 including one or more memory cells 16. FIG. 1 also shows plural metal contacts 5a, 5b, and 5c used for electrical interconnetion. The peri-transistor region 12 may be seen to include a peripheral circuit transistor 18 having a gate formed of a second conductive layer 22a and a first conductive layer 20a, and cell array region 14 may be seen to include the one or more memory cell 16 having a control gate 22b and floating gate 20b. 
FIGS. 2 through 5 are cross-sectional views of the related art structure taken generally along the line X-Xxe2x80x2 of FIG. 1.
As shown in FIG. 2, the first conductive layer is formed of a first polysilicon layer 24, which may be seen to overlie a field oxide layer 26, which in turn will be understood to overlie a substrate 1.
As shown in FIG. 3, an interlayer insulating layer 28 typically is formed of a first oxide film/silicon nitride film/second oxide film (ONO) to overlie the field oxide layer 26. A second conductive layer is formed as a stacked layer of a second polysilicon layer 30a and a tungsten silicide layer 30b on the interlayer insulating layer 28. Finally, a mask oxide layer 32 is formed to overlie the second conductive layer. The memory cell gate 20b, 22b and the peripheral circuit transistor gate 20a, 22a are formed by patterning the mask oxide layer 32 and the second conductive layer and first conductive layer. Source/drain regions 70, 80 of the memory cell transistor 16 are formed adjacent the memory cell gate 20b, 22b. Source/drain regions (not shown) of peripheral circuit transistor 18 are formed on the substrate 1.
A butting contact typically is formed next as part of a patterning step shown in FIG. 4. The butting contact will be understood to provide for directly applying a voltage to a first conductive layer (first portion) 20a of the peripheral circuit transistor gate 20a, 22a. 
FIG. 4 illustrates a first step of formation of the butting contact area 34 in the peri-transistor region 12 of the memory device whereby a predetermined portion of the mask oxide layer 32, the tungsten silicide layer 30b and the polysilicon layer 30a are selectively removed.
At the same time, i.e. during formation of the butting contact of peri-transistor region 12, the fuse 11 of passive device region 10 is formed by patterning the second conductive layer.
In FIG. 5, it may be seen that a first silicon nitride layer 36, a first interlayer dielectric (ILD1) layer 38, a second silicon nitride layer 40 (which acts as an etching stopper layer) and a second interlayer dielectric (ILD2) layer 42, are sequentially formed over the passive device region 10, peri-transistor region 12 and cell array region 14 of the memory device. One or more contact holes, for providing electrical connection to the gate and the fuse, are formed by etching the first and second ILD1, ILD2 layers 38, 42, the first and second silicon nitride layers 36, 40 and, at least in part, the mask oxide layer 32.
Unfortunately, during etching of the ILD1 layer 38, 42 and the silicon nitride layers 36, 40 to form a contact hole, the surface of the fuse 11 may not entirely open. This is because of the step difference between the fuse 11 and the gates 22a, 22b, which two features may be seen to lie in two parallel planes at different elevations above the substrate. This step difference is most clearly seen near the middle of the structure shown in FIG. 3. The surface of the tungsten silicide layer of the gate 22a that is at an elevation higher than that of the fuse 11 is opened prior to exposing the surface of the tungsten silicide layer that forms the fuse 11. As a result, the contact hole 5a for the fuse 11 is not completely opened.
Thus, the electrode or conductive path 55a formed in the metal contact hole 5a may fail to connect to the fuse 11, as illustrated in passive device region 10 of FIG. 5. The reliability of the memory device is thus degraded, as will be described in further detail below.
FIG. 5 illustrates the final related art steps of forming other conductive paths 55b and 55c. The steps may be seen to include depositing the first silicon nitride layer 36, the ILD1 layer 38, the second nitride stopping layer 40 and the second ILD layer 42 over the entire surface of the memory device including the passive device region 10, the peri-transistor region 12 and the cell array region 14 and then filling patterned contact holes 5b, 5c etched therethrough with conductive material to form plural conductive paths 55b, 55c. 
It may be seen from FIG. 5 that the conductive paths 55a, in the passive device region 10 in which fuse 11 is formed, do not reach the tungsten silicide layer 30b. This is because an intervening thin oxide layer remainsxe2x80x94between the conductive paths 55a and the tungsten silicide layer 30bxe2x80x94that covers, and thus fails to fully expose, the tungsten silicide layer 30b, at an area indicated by C in FIG. 5 due to the step difference between the fuse 11 and the gate 22a as discussed above.
Accordingly, in accordance with related art processes and structures, electrical contact is inhibited and often prevented. This is the source of the reliability problems mentioned above in memory and other semiconductor devices.
The present invention provides a reliable contact to a passive device region of an integrated circuit device, the passive device being, for example, a resistor, an inductor, or a fuse for disabling selected circuit portions, e.g. by laser-blowing or the like. Adjacent, spaced, elevated, so-called dummy pattern (shoulder) regions are formed under the portions of the passive device on which the contact hole is formed. The shoulder region is formed of the same material as the first conductive layer of the gate of the peripheral transistor. Contact holes may be formed that extend reliably through interlayer dielectric layers over the passive device, to the integrated passive device. Therefore, the electrodes may be formed through the contact holes to be a reliable contact to the integrated passive device.